The present invention relates to a method and apparatus for calculating a delay time for a logic circuit with high accuracy and to a method of calculating delay data for a delay library.
In an integrated circuit, different power-source voltages may be applied intentionally to an external power-source terminal and to an internal circuit thereof with a view to improving the characteristics of the integrated circuit. However, as a higher-speed integrated circuit with a smaller feature size has been implemented, parasitic are produced therein so that different power-source voltages are applied unintentionally to the external power-source terminal and to the internal circuit.
The following are two conventional embodiments in which different power-source voltages are applied intentionally and unintentionally.
(First Conventional Embodiment)
To reduce the power consumption of an integrated circuit or increase the operating speed thereof, a power-source voltage applied to an internal circuit block may be used selectively. For example, a circuit block which should be reduced in power consumption is supplied with a voltage lower than a power-source voltage applied to a power-source terminal, while another circuit block which should operate at a higher speed is supplied with the power-source voltage equal to the external power-source voltage. In thus designing the integrated circuit, it is necessary to create a gate-level delay library for each of the power-source voltages and selectively use a desired delay library in order to verify a delay in signal propagation for the integrated circuit and the operation thereof.
(Second Conventional Embodiment)
When a consumed current flows through a power-source line (hereinafter referred to as a VDD line) for supplying a power-source potential to a circuit block in an integrated circuit and through a ground line (hereinafter referred to as a VSS line) for supplying a ground potential, a wiring parasitic composed of resistance (R), capacitance (C), and inductance (L) emerges at the VDD or VSS line and causes a voltage variation. For the sake of simplicity, it is assumed here that the parasitic on the power-source line is composed only of, e.g., resistance. Since the power-source voltage effectively applied to the circuit block is reduced by the voltage variation resulting from the wiring resistance, a delay time is increased accordingly. However, a conventional method of calculating a delay is disadvantageous in that the error between the result of analysis and the result of measurement is increased because of postulated ideal VDD and VSS lines which undergo no variation in power-source voltage applied thereto.
To prevent the error from being increased, e.g., Japanese Laid-Open Patent Publication HEI 6-124318 has disclosed a simulation method wherein the resistance of a power-source line is calculated by a data extracting unit, a process-parameter storing unit, and a power-source-voltage storing unit, while a drain current in a MOSFET as a gate element is calculated by a gain-coefficient calculating unit and a drain-current calculating unit. After a voltage drop on the power-source line is calculated by using the resistance on the power-source line and the drain current, a delay time is calculated by a propagation delay calculator from the gain coefficient .beta. of the drain current and an incidental capacitance.
(Problems Associated with First Conventional Embodiment)
As mentioned above, since the delay-data extracting process of obtaining desired delay data from the cell library is based on the setting of the power-source voltage at a specified value, it is necessary to repeatedly extract delay data a number of times equal to the number of different power-source voltages. With a multi-input gate such as a multi-bit adder cell, extraction time is elongated and hence the time required to design a cell library is elongated disadvantageously. In addition, a power-source voltage in consideration of an optimum delay time has been incompatible with a power-source voltage in consideration of optimum power consumption.
(Problems Associated with Second Conventional Embodiment)
Japanese Laid-Open Patent Publication HEI 6-124318 shown in the second conventional embodiment has not disclosed the relationship between the gain coefficient .beta. and the delay time in the propagation delay calculator, which is an important factor in calculating the dependency of the delay time on the power-source voltage and has not shown a specific method of calculating a delay time.
To analyze the delay time based on the dependency of the gain coefficient .beta. on the power-source voltage, there has been proposed a method of calculating the time required to charge or discharge a load capacitance or load resistance based on the voltage-dependency of a drain current in a MOSFET by a transistor-level or switch-level circuit simulation. However, the method is not practical since it uses a transistor-level netlist containing an increased number of circuit components as the target of the circuit simulation and therefore considerably long time is required by a large-scale circuit.
To calculate the dependency of the delay time on the power-source voltage, there has been proposed a method of multiplying the delay time by a coefficient indicative of the dependency of the delay time on the power-source voltage, which has been calculated previously. There has also been proposed a method of calculating a plurality of effective power-source voltages from which potentials corresponding to variations in power-source voltage on the VDD and VSS lines have preliminarily been reduced under each of the operating conditions and using the delay values extracted for the respective power-source voltages, as described in the first conventional embodiment. In the foregoing methods, however, the effective power-source voltages should be predetermined and it is impossible to reliably analyze the influence of voltage variations on different power-source lines produced in each of the circuit blocks in an actual integrated circuit, including a plurality of circuit blocks connected to power-source lines at different voltages and circuit blocks operating at different frequencies.
With an integrated circuit having internal circuit blocks operating at different power-source voltages, as used in the first conventional embodiment, a delay for the whole integrated circuit cannot be calculated by the method in which the coefficient indicative of the dependency of the delay time on the power-source voltage is used as a multiplier factor without distinction.